Exemplary embodiments relate to a semiconductor memory device and a method of operating the same and, more particularly, to a semiconductor memory device and a method of operating the same, which are capable of improving the operating speed.
The memory cells of a DRAM or flash memory device are often coupled to a sense amplifier or a page buffer for storing or sensing data through a bit line. As an example of a DRAM memory device, a NAND flash memory device is described below in detail.
In FIG. 1, for a NAND flash memory device according to an example, a memory array includes 1024 to 4096 memory blocks. Each of the memory blocks includes a plurality of strings. Each of the strings includes a drain select transistor coupled to a bit line, a source select transistor coupled to a common source line, and memory cells coupled in series between the drain select transistor and the source select transistor. In each memory block, the strings placed in the same column are coupled to the page buffer through one bit line.
In order for one bit line to couple the strings of the same column in all memory blocks to the page buffer as described above, the length of the bit line becomes long.
In an operation of reading data stored in a memory cell or a verification operation of detecting the threshold voltage of the memory cell, a step of precharging a bit line is performed. With an increase of the length of the bit line, the time taken to precharge the bit line may be increased. Accordingly, the entire operation time may be longer.